The Peripheral Interconnect Special Interest Group (PCI-SIG) industry forum has announced revision 7.0 of its interface standard which is set to double the maximum data transfer rate of devices built to revision 6.0.
With 128 giga-transactions per second (128 GT/s), PCIe 7.0 is specified to provide a per-lane speed of 32 gigabytes per second.
In 16-lane configurations, this equates to 512 Gbps, up from 256 Gbps in PCIe 6.0, which was released in January this year.
Like PCIe 6.0, revision 7.0 uses four-level pulse amplitude modulation (PAM4) signalling with 1b/1b flit mode, as opposed to PAM2 non-return-to-zero (NRZ) with 128b/130b in earlier versions of the standard.
Backwards compatibility with previous generations of PCIe technology is a feature goal of revision 7.0, along with improved power efficiency.
However, greater component complexity with shorter PCIe traces could result in higher motherboard pricing to support revision 7.0 devices.
PCI-SIG has around 900 members, and expects the new standard to come into effect by 2025, with devices built to it after 2028.
